1. Field
Exemplary embodiments of the present invention relate to a data sensing circuit and a memory device including the same.
2. Description of the Related Art
Memory devices and diverse integrated circuits use a data sensing circuit for sensing data. The data sensing circuit is to sense data even though the data have a small difference between a logic high level and a logic low level thereof and the logic value of the data may not be easily detected.
FIG. 1 is a schematic diagram of a bit line sense amplifier, which is a data sensing circuit used in a conventional memory device.
When a data is read out of a memory cell 101, the voltage level of a bit line BL is changed based on the read data. Since the voltage level change of the bit line BL is very slight, the voltage level of the bit line BL is amplified by a bit line sense amplifier 110. A precharger 120 shown in the drawing is a structure for precharging bit lines BL and /BL to a voltage level of a precharge voltage VBLP before data are loaded on the bit lines BL and /BL.
The bit line sense amplifier 110 may be disposed at the ends of bit lines BL and /BL and formed of a latch circuit for amplifying the voltage difference between a pair of bit lines BL and /BL. The latch circuit includes two inverters 111 and 112. When the bit line sense amplifier 110 performs a data sensing operation, a driving voltage is supplied thereto. For example, a pull-up voltage, which is a power supply voltage VDD or a core voltage VCORE, is supplied to a pull-up voltage supplier RTO, while a pull-down voltage, which is a ground voltage, is supplied to a pull-down voltage supplier SB. Upon receipt of the driving voltage, the inverters 111 and 112 amplifies the voltage difference between the pair of bit lines BL and /BL.
For example, when the voltage level of the positive bit line BL is a little higher than the voltage level of the negative bit line /BL, the bit line sense amplifier 110 makes the positive bit line BL to have the pull-up voltage level and the negative bit line /BL to have the pull-down voltage level. Conversely, when the voltage level of the negative bit line /BL is a little higher than the voltage level of the positive bit line BL, the bit line sense amplifier 110 makes the negative bit line /BL to have the pull-up voltage level and the positive bit line BL to have the pull-down voltage level.
To accurately sense the data loaded on the pair of the bit lines BL and /BL in the bit line sense amplifier 110, PMOS transistors and NMOS transistors that constitute the bit line sense amplifier 110 are to be fabricated all the same. However, it is difficult to fabricate all of the transistors of the bit line sense amplifier 110 to be the same and the transistors may have different characteristics from each other.
Therefore, the conventional bit line sense amplifier 110 has an offset, i.e., a deviation, in operations of the transistors, and technologies such as a method of increasing capacitance of the memory cell 101 or a method of increasing the driving voltage level of the bit line sense amplifier 110 have been used to reduce the offset. However, the method of increasing capacitance of the memory cell 101 may increase the area of the bit line sense amplifier 110, and the method of increasing the driving voltage level of the bit line sense amplifier 110 may increase current consumption.